This invention relates to a chip-to-chip communication system. Chip-to-chip communication systems facilitate interactions between a number of devices. Typically the devices communicate with each other via a bus or a plurality of signal lines.
The term “chip-to-chip” refers to any implementation where a number of devices are inter-coupled together. The term “device(s)” is used to refer to one or more integrated circuits or cards which may include synchronous dynamic random access memories (SDRAM), double data rate (DDR) memories, micro-controllers, processors, memory modules, modem cards, and video cards, just to name a few. A memory system and computer system are ready examples of a chip-to-chip communication system formed from an inter-coupled group of integrated circuits or cards. The usage of the term “bus” refers to any arrangement of a plurality of conducting medium used to transport information between devices. Such conducting medium may be implemented in one of many ways including wires in a flex tape or patterned conducting lines on a printed circuit board, etc. For our purposes, one of a conducting medium used in a bus of a chip-to-chip communication system will hereinafter be referred to as a “signal line.”
Thus, in keeping with the foregoing, an example of a conventional chip-to-chip communication system is illustrated in FIG. 1. Here, chip-to-chip communication system 10 includes master device 20 and a plurality of slave devices 30a to 30n, coupled by at least one signal line 40. In this example, the master device 20 may be any device capable of communicating with one or more other master devices (not illustrated) or with slave devices 30. Typically, slave devices 30a-n only respond to commands given by master device 20, and do not communicate with each other. More specific examples of chip-to-chip communication systems include a memory system having a controller directing interactions with a number of memory devices over a bus, or a computer system having a mother board with a central processing unit (CPU) communicating with a number of peripheral device cards.
One common class of slave devices includes memory devices, such as dynamic random access memory (DRAM). Such devices are characterized by limited access speeds. Access speeds for conventional DRAMs have significantly lagged behind the operating speeds pioneered in conventional CPUs. Thus, designers face a constant challenge in the development of memory systems having sufficiently high data throughput to fully utilize CPU performance capability.
With reference to FIG. 2, a chip-to-chip communication system implemented as a conventional memory system 45 is illustrated. Here, a controller 50 and a number of memory devices 60 are disposed on a circuit board (not illustrated). The memory devices 60 are directly coupled in parallel to the controller 50 over a wide bus 70. In this example, each memory device 60 has a dedicated portion of signal lines 80 directly coupled to the controller 50. In more detail, each memory device 60 is coupled to eight signal lines and all sixty four signal lines of wide bus 70 are coupled to controller 50.
It is well known that by utilizing this parallel approach to couple memory devices to the controller, the data throughput of the chip-to-chip communication system 45 may be improved. However, the width of the bus is limited by physical constraints, i.e., the available space and layout area of the circuit board. Thus, achieving additional data throughput by widening the bus (i.e., increasing the number of signal lines) has a maximum feasible limit.
Many different techniques have been employed in attempts to increase the data throughput of the conventional memory system. One attempt uses a relatively narrow bus and faster information transfer rates. “Information” in this context refers broadly to data, control and/or address information.
With reference to FIG. 3, a chip-to-chip communication system employing a relatively narrow bus is shown. In this example, a plurality of memory devices 105, are directly coupled to a controller 110 via narrow bus 115. Bus 115 comprises relatively few signal lines as compared to the parallel architecture of FIG. 2. This later conventional approach does not utilize a parallel architecture to achieve high data throughput. Thus, physical constraints tend to be less of a concern. Rather, in this conventional approach, controller 110 and memory devices 105 incorporate high speed interfaces. Here, high data throughput is achieved by transferring information between the controller and the memory devices at high transfer rates.
As information transfer rates are increased over a signal line, difficulties arise which impose a practical upper limit on these higher rates. With reference to FIG. 4A, a chip-to-chip communication system is shown having a signal line 220 coupling a plurality of devices 230a to 230c. The plurality of devices 230a to 230c are “directly coupled” to the signal line 220 at locations 240a to 240c. Two adjacent locations 240a and 240b span distance “d” to define a plurality of line segment 210a to 210d. Each line segment 210a-d may represent a common pitch between devices 230a to 230c. The term “directly coupled” refers to an electrical connection between a plurality of input/output (I/O) interface circuits 242a to 242c and signal line 220.
In this example, one line segment 210 is a conductor which may be modeled by electrical elements as shown in line segment model 250. The elements in the line segment model 250 describe the electrical behavior of each signal line segment. This electrical behavior is practically unnoticeable and therefore irrelevant at lower information transfer rates but becomes more significant to system performance as rates are increased. It is known to those skilled in the art that disposing a plurality of devices at equidistant points along a signal line causes the signal line to behave as multi pole low pass filter.
As the length “d” of the line segments 210a-d is decreased, the effective maximum operation frequency decreases. With reference to FIG. 4B, a representational graph of the signal line frequency response of the conventional chip-to-chip communication system with respect to three device I/O spacings is illustrated. Graph 410 depicts signal amplitude over a range of effective operation frequencies for signal line 220 (FIG. 4A) as a function of three device spacings d1, d2, and d3. Graph 410 illustrates three decreasing device I/O spacings d1, d2, and d3 and correspondingly decreasing cutoff frequency curves 412, 414, and 416.
With further reference to FIG. 4A, a plurality of “interface conductors” 255a to 255c typically couples each of interfaces 242a to 242c on devices 230a to 230c and signal line 220. The term “interface conductor” denotes all structures coupled to interfaces 242a to 242c and the signal line at location 240a to 240c. For example, interface conductors 255a-c might include bond wires, pins, modules or circuit card connectors, ball bonds, bond pads, electrostatic discharge protection devices, driver and receiver circuits and related interconnects. The interface conductors 255a-c, similar to the line segments 210a-d, may be modeled using electrical elements as shown in an interface conductor model 260. The electrical elements in interface conductor model 260 generally describe electrical behavior associated with the interface conductor 255.
When operating at high data transfer rates, the electrical behavior of the system depends, to a significant extent, upon the practical and physical attributes of the line segments 210 and the interface conductors 255. Here, the line segment model 250, includes inductive component 265, capacitive components 270 and resistive components 275. Interface conductor model 260 includes inductive component 280, capacitive component 285 and resistive component 290. It is well known by those skilled in the art that components such as the resistive components 290 and 275 introduce losses. The term “losses” may be used to describe mechanisms by which information transfer is not efficiently executed. Losses impose a limit on the rate at which the information may be reliably transferred. The magnitude of these losses are a function of the information transfer rate. As the information transfer rate is increased, losses also increase.
Interface conductor model 260 includes inductive component 280, capacitive component 285 and resistive component 290. These elements are directly coupled to the signal line 220 and, thus, become effectively “part” of signal line 220. Losses resulting from resistive component 290 increase as more devices are coupled to the bus.
With reference to FIG. 4A and FIG. 4C, a representational graph of the signal frequency response of the conventional chip-to-chip communication system with respect to three levels of dissipative loss is illustrated. Sources of dissipative loss include printed circuit board substrate, skin effect resistance of metal traces of the signal lines, and input resistance seen at the device I/O. Graph 420 indicates signal amplitude over a range of effective operation frequencies for signal line 220 (FIG. 4A) as a function of different quantities of dissipative loss. In the conventional chip-to-chip communication system, cutoff frequency decreases as the amount of dissipative loss decreases.
The capacitive component 285 plays a role in limiting the maximum useful information transfer rate. As the device input capacitance C1 of capacitive component 285 is decreased, the maximum effective information transfer rate supported by the signal line increases. A representational graph of the signal frequency response of the conventional chip-to-chip communication system with respect to three device input capacitances is illustrated in FIG. 4D. Device input capacitance C1 is inherent in elements of the I/O structures disposed on each device. These elements include, for example, bond pads, electrostatic discharge devices, input buffer transistor capacitance, and output driver transistor parasitic and interconnect capacitances relative to the device substrate. Typically, the input capacitance is present between a ground potential (not shown) and the signal line. Graph 430 depicts signal amplitude over a range of effective operation frequencies for signal line 220 (FIG. 4A) as a function of three input capacitances C1, C2, and C3 (where C1<C2<C3). In the conventional chip-to-chip communication system, cutoff frequency decreases as the device input capacitance decreases. Graph 430 illustrates the three input capacitances C1, C2, C3 and correspondingly decreasing cutoff frequency curves 432, 434, and 436.
As a result, the components of the interface conductor model adversely effect the maximum rate of information transfer. Here, as the information transfer rate increases, the magnitude of the losses associated with these components increases accordingly. The losses associated with these components impose an effective maximum information transfer rate limit.
In the conventional chip-to-chip communication system of FIG. 2, a parallel approach was used to achieve high data throughput. The information transfer rate in such systems tended to be too low for the loss components of the foregoing models to have any adverse effect on system performance.
In the narrow bus approach, the information transfer rate is increased relative to the information transfer rate employed in the parallel approach. The inductive, capacitive and resistive components in the interface conductor model and line segment model become more significant in determining the reliability of information transfer when the information transfer rate is increased. The resistive components in the interface and line segment models tend to degrade the integrity of the information in some proportion to the rate of information transfer.
One attempt to address the issue of increasing the speed of a data communications network, is described in U.S. Pat. No. 3,619,504. This patent describes a high speed network which employs coupling elements to couple information between a transmission line and receiver circuit. The coupling elements induce currents in “stub” lines which are terminated by a resistor. In operation, a voltage transition propagates down the transmission line and induces a current (in the opposite direction) in a stub line of each coupling element. An inductive coupling technique and associative circuit are employed to couple information between the transmission line and receiver circuit. The inductive coupling technique typically requires a stub line having a suitable length to facilitate current induction via the coupling element. This tends to impose a physical limit upon the interface between the receiver circuit and the transmission line and may be unsuitable for applications requiring tight space requirements. Thus, the inductive coupling technique may be limited by a minimum pitch requirement between adjacent receiver circuits due to the length of the stub line in each coupling element.
In sum, conventional chip-to-chip communication systems have employed a parallel approach to increase information throughput. However, use of this parallel approach is severely limited by space constraints. To overcome the limitations of the parallel approach, some conventional chip-to-chip communication systems have employed a narrow bus approach in which a high speed interface is incorporated into the devices. Here, high throughput is achieved by a high rate of information transfer. However, as the information transfer rate increases; inductive, capacitive and resistive components become significant limiting factors to the effective transfer of information. As the information transfer rate is increased, the magnitude of these components increases. This tends to impose an upper limit on the information transfer rate. In the conventional chip-to-chip communication system, the maximum effective operation frequency (or cutoff frequency) decreases as the pitch between adjacent device I/O are decreased. An inductive coupling technique may be viable towards increasing the effective information transfer rate in a chip-to-chip communication, but a minimum pitch requirement may be imposed between adjacent devices due to the required length of stub lines to effectuate inductive coupling.
Accordingly, there is a need to minimize the impact of losses resulting from the resistive component of the interface conductor model. Resistive components, inductive components, and capacitive components increasingly limit the reliability of information transfer as the information transfer rate is increased.
There is a need to provide circuits and techniques for increasing the effective information transfer limit beyond present maximum information transfer rates in conventional chip-to-chip communication systems. By increasing the maximum rate of information transfer further, data throughput may be increased, and higher system performance realized.